Compact Physical Model for Power Supply Noise

The aggressive scaling of CMOS integrated circuits §makes the design of power distribution networks a §serious challenge. This is because the supply §current and clock frequency are increasing, which §increases the power supply noise. Excessive power §supply noise can lead to severe degradation of chip §performance and even logic failure. Therefore, power §supply noise modeling and power integrity validation §are of great significance in GSI systems and 3-D §systems. Compact physical models enable quick §recognition of the power supply noise without doing §dedicated simulations. In this book, accurate and §compact physical models for the power supply noise §are derived for power hungry blocks, hot spots, 3-D §chip stacks, and chip/package co-design. The impacts §of noise on transmission line performance are also §investigated using compact physical modeling §schemes. The models can help designers gain §sufficient physical insights into the complicated §power delivery system and tradeoff various important §chip and package design parameters during the early §stages of design. The models are compared with §commercial tools and display high accuracy.